1. Field of the Disclosure
The present disclosure generally relates to semiconductor devices, and more specifically to native p-type metal oxide silicon (PMOS) devices having low threshold voltage and high drive current.
2. Background Art
Metal oxide semiconductor field effect transistor (MOSFET) devices are generally fabricated using conventional complementary metal oxide silicon (CMOS) foundry technology. The conventional CMOS logic foundry technology accommodates a minimum size, such as a length, width, and/or height of the regions of the semiconductor devices as defined by one or more minimum design rules (MDRs). These minimum design rules represent limits to resolution of processing used by the conventional CMOS logic foundry technology, such a minimum space interval between one or more photolithographic masks used to manufacture the semiconductor devices.
A conventional MOSFET device generally includes a source region, a drain region, a gate between the source and drain regions, and a channel region below the gate region. A minimum voltage, called the threshold voltage, is required at the gate for the device to turn “on”. A drive current, also referred to as a drain current, flows between the source and drain regions through the channel region when a gate potential above the threshold voltage is applied, and potentials at the source and drain regions are applied. MOSFET devices can be fabricated to be P-type or N-type devices. A P-type metal oxide semiconductor field effect transistor (PMOSFET) device, for example, can be fabricated by implanting phosphorus atoms into a P-type substrate to create an N-well. P+ regions are formed in the N-well to provide source and drain regions. A PMOSFET device may be interchangeably referred to herein as PMOS device or PMOSFET device.
With the advance in semiconductor technology and the increasing need for high speed systems with low power consumption, there has been continued scaling down of MOSFET devices using CMOS foundry technology with decreasing MDRs to accommodate a larger number of MOSFET devices on smaller systems. However, the scaling down of MOSFET devices to smaller dimensions can introduce short channel effects in the devices due to the short channel lengths (about approximately 100 nm or less) of the scaled down MOSFET devices. Short channel effects can cause degradation in the performance of the MOSFET device due to, for example, but not limited to the loss of gate control over the threshold voltage which can result in the device being mostly in the “on” state and the degradation of carrier mobility which results in lower drive current.
The foregoing problem with the threshold voltage has been addressed in U.S. patent application Ser. No. 10/911,720, filed on Aug. 5, 2004, now U.S. Pat. No. 7,161,213 and U.S. patent application Ser. No. 11/648,651, filed on Jan. 3, 2007, now U.S. Pat. No. 7,382,024, all of which are incorporated herein by reference in their entirety. In the aforementioned applications, a conventional native PMOS device having a low threshold voltage has been described. The conventional native PMSO device includes a P+ polysilicon gate, halo implants, lightly doped regions in the source and drain regions, and heavily doped regions in the source and drain regions. The halo implants and the doped regions of the source and drain regions primarily enable low threshold voltage characteristics of the conventional native PMOS device.
With the continued scaling down of MOSFET devices, there is still an ongoing need for a MOSFET device that maintains a stable threshold voltage and exhibits a high drive current over a varying range of short channel lengths. At the same time, for a MOSFET device to have a large operating voltage range, it is necessary for the threshold voltage to be close to zero volts.
The present disclosure will now be described with reference to the accompanying drawings. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost digit(s) in the reference number.